Domino logic circuits have been used in modern high performance microprocessors because of the superior speed and area characteristics of the dynamic circuits as compared to the static CMOS circuits. However, the domino logic gates used in the domino logic circuit typically consume more dynamic switching power and display weaker noise immunity as compared to the static CMOS gates used in the static CMOS circuits.
The domino logic circuits may include: (1) a precharge circuit that pre-charges one or more nodes in the circuit to a predetermined value; (2) a keeper circuit that keeps or maintains the node in the circuit at the predetermined value; (3) an input circuit that inputs one or more signals and that determines the value to output on the output circuit; and (4) an output circuit.
One example of a two-stage domino circuit is shown in FIG. 1. The pre-charge circuit comprises a pull-up transistor (pull-up). When the Clk signal goes low, the dynamic note is precharged via the pull-up transistor to approximately VDD (such as VDD−0.7V). After the Clk signal goes high, the dynamic node may decrease due to leakage current, such as leakage via the input circuit. In order to maintain the dynamic node at its precharged value, a keeper circuit (keeper) may be used. One example of a keeper circuit, with an inverter in combination with a switch, is illustrated in FIG. 1. The domino circuit may also include an input circuit, which may include logic for inputting one or more signals and determining the value to output on the output circuit. Any logic may be used for the input circuit including OR, AND, NAND, NOR, XOR, etc. For example, FIG. 1 shows an OR input circuit whereby if In1 or In2 is high, the input circuit pulls down the dynamic node to approximately ground. The domino circuit may further include an output circuit. The output circuit may, at its input, be connected to or in communication with the dynamic mode, and at its output, be connected to the next stage of the circuit. For example, the output of the output circuit may be connected to the next stage of the domino logic circuit, such as shown in FIG. 1.
In the MOS technologies with a gate insulator thicker than 20 Å, the gate oxide leakage current (Igate) may be orders of magnitude smaller than the subthreshold leakage current. Therefore, the Igate has typically been ignored in the previous MOS technologies. Igate may be caused by the direct tunneling of the electrons and holes through the insulating gate dielectric layer. The tunneling probability of carriers may increase dramatically with the scaling of the gate oxide thickness (tox) in each new technology generation. The tox is in the range of 12 Å to 16 Å in the current MOS technologies. Such a thin tox may lead to a significant gate tunneling current. Particularly at the low die temperatures during long idle periods, most of the power consumption may occur due to gate oxide leakage.
FIG. 1 attempts to reduce the leakage current using three low-Vt/high-Vt sleep transistors. In the figures, the high-Vt transistors are represented by a thick line in the channel region. As shown in FIG. 1, NMOS/PMOS sleep switches are utilized to force both the dynamic and output nodes of a domino logic circuit into a low voltage state in the standby mode. Two low-Vt NMOS sleep transistors N1 and N2 are located at both the dynamic and output nodes, respectively, as illustrated in FIG. 1.
In the active mode, the sleep signal is set low. The circuit shown in FIG. 1 thus operates in the active mode similarly to a standard domino logic circuit. In the standby mode, the clock may be gated high. The sleep signal is set high, thereby turning on N1 and N2. The dynamic and output nodes are discharged through N1 and N2, respectively. P3 is cut-off to avoid a static DC current path through P4 and N2. Two additional examples of domino logic circuits with the NMOS/PMOS sleep switch technique are shown in FIGS. 2 and 3. FIG. 2 depicts a schematic of a footless NMOS/PMOS sleep switch dual-Vt domino gate. FIG. 3 depicts a schematic of a footed NMOS/PMOS sleep switch dual-Vt domino gate. Specifically, NMOS transistor N3 acts to make the circuit footed.
While the circuits depicted in FIGS. 1-3 reduce leakage current, they require additional area for the three sleep transistors. Thus, there is a need to reduce the leakage currents, particularly in the context of domino logic circuits, using less circuit area.